1. Field of the Invention
The present invention generally relates to multiple frame rate synchronous detecting methods and apparatuses and more particularly, to multiple frame rate synchronous detecting method and apparatus which receives and synchronous-detects data having any one frame rate among a plurality of predetermined frame rates.
2. Description of the Related Art
In SONET (Synchronous Optical Network) system used in North America, Taiwan, Hong Kong, and SDH (Synchronous Digital Hierarchy) used in other countries, multiple frame rates are defined.
SONET system adopts three synchronous transmission modules shown in FIG. 1. The first one is a synchronous transmission module STS-48 (communication speed of 2.48832 Gbps, about 2.4 Gbps) having a frame format shown in FIG. 1(A). The second one is a synchronous transmission module STS-12 (communication speed of 622.08 Mbps, about 622 Mbps) having a frame format shown in FIG. 1(B). The third one is a synchronous transmission module STS-3 (communication speed of 155.52 Mbps, about 156 Mbps) having a frame format shown in FIG. 1(C).
The STS-48 frame comprises SOH (Section OverHead) of 9 rows×144 columns and pay-load of 9 rows×4176 columns. A1 and A2 bytes each having 48 bytes on the first row are frame synchronous signals. Among these bytes, the last two bytes (#47, #48) in the A1 bytes and the first two bytes (#49, #50) in the A2 bytes have a fixed frame detection pattern of 0xF6F62828 (0x represents hexadecimal notation).
The STS-12 frame comprises SOH (Section OverHead) of 9 rows×36 columns and pay-load of 9 rows×1044 columns. A1 and A2 bytes each having 12 bytes on the first row are frame synchronous signals. Among these bytes, the last two bytes (#11, #12) in the A1 bytes and the first two bytes (#13, #144) in the A2 bytes have the fixed frame detection pattern of 0xF6F62828 (0x represents hexadecimal notation).
The STS-3 frame comprises SOH (Section OverHead) of 9 rows×9 columns and pay-load of 9 rows×261 columns. A1 and A2 bytes each having 3 bytes on the first row are frame synchronous signals. Among these bytes, the last two bytes (#2, #3) in the A1 bytes and the first two bytes (#4, #5) in the A2 bytes have the fixed frame detection pattern of 0xF6F62828 (0x represents hexadecimal notation).
FIG. 2 shows a block diagram of a frame synchronous detecting apparatus in the prior art. An O/E module 10 receives an optical signal having a single frame rate, converts it to an electrical signal and outputs serially. Frame data (fixed rate at iMbps) outputted from this O/E module 10 is supplied to a serial/parallel converting circuit (S/P) 12 having a ratio of 1:2, and converted there to an n-bit parallel signal (fixed rate at i/n Mbps×n) and supplied to a synchronous detection circuit 14.
The synchronous detection circuit 14 keeps in store a 32 bit fixed pattern (0xF6F62828) for synchronous detection of section overhead A1 bytes and A2 bytes in the synchronous transmission module, and compares the stored pattern with a bit sequence received in parallel to detect the frame pattern. When the synchronous detection circuit 14 detects the frame pattern, it outputs data sequence and a frame detection signal (SEL). A barrel shift part 16 receives and shifts the data sequence in response to an input time of the frame detection signal to output data sequence as shown in FIGS. 1(A), 1(B) and 1(C) and a frame pulse (FP).
In the prior art apparatus for handling data having multiple frame rates, different synchronous detection circuits are provided for processing different frame rates, and an adequate synchronous detection circuit is selected to be used depending on a frame rate of received data.
FIG. 3 shows a block diagram of one example of such prior multiple frame rate synchronous detection apparatuses. An O/E module 20 converts a frame data of a received optical signal to an electrical signal and outputs it serially. A control circuit 21 receives the frame data signal and directs it to one of serial/parallel converting circuits 22A, 22B and 22C. The control circuit 21 directs the frame data signal to the serial/parallel converting circuit 22A when the control signal indicates STS-48. The control circuit 21 directs the frame data signal to the serial/parallel converting circuit 22B when the control signal indicates STS-12. The control circuit 21 directs the frame data signal to the serial/parallel converting circuit 22C when the control signal indicates STS-3.
The serial/parallel converting circuit 22A converts 2.4 Gbps frame data to n-bit parallel data in synchronism with a clock of 2.4 GHz frequency, and supplied the converted parallel data to a synchronous detection circuit 24A. The serial/parallel converting circuit 22B converts 622 Mbps frame data to n-bit parallel data in synchronism with a clock of 622 MHz frequency, and supplied the converted parallel data to a synchronous detection circuit 24B. The serial/parallel converting circuit 22C converts 156 Mbps frame data to n-bit parallel data in synchronism with a clock of 156 MHz frequency, and supplied the converted parallel data to a synchronous detection circuit 24C.
Each of the synchronous detection circuits 24A, 24B and 24C keeps a 32-bit synchronous detection pattern (0xF6F62828) in store, compares the stored pattern with the bit sequence received in parallel to detect the frame pattern, and outputs a data sequence (data) and a frame detection signal (SEL).
In this manner, the prior art multiple frame rate synchronous detection apparatuses had to be equipped with a plurality of serial/parallel converting circuits having different speeds and a plurality of synchronous detection circuits for processing different frame rates, and therefore resulted in large circuit sizes.